Integrated circuits (ICs) can include a large number of interconnected devices, such as transistors, capacitors and resistors, that are formed on the same semiconductor substrate. One the great advantages of ICs is the uniformity of the various devices making up the integrated circuit. By fabricating hundreds or thousands of such devices with the same series of process steps, absent a processing defect, the various devices within the IC will operate in a generally uniform manner.
The uniformity of device response can be particularly advantageous in semiconductor memory ICs. Semiconductor memory ICs can include thousands of memory cells, each of which can store one or more data bits. By manufacturing memory cells having uniform responses, data can be stored and read from the memory cells in a predictable manner. For example, a single amplifier circuit is typically used to read data from, or write data into, a number of memory cells on a semiconductor memory IC. In a typical dynamic random access memory (DRAM), a single sense amplifier is used to read or write data for memory cells in a column of memory cells. If the characteristics of the memory cells varied in any significant manner, the sense amplifier response could also vary, and possibly result in an erroneous reading or writing operation.
While a semiconductor memory IC can be fabricated to provide uniformity in memory cell response, as semiconductor IC sizes increase, memory cell responses may be affected by the memory cell's particular position within the IC, due to variations in timing signals.
One particular example of a timing delay which affects memory cell response is set forth in FIG. 1. FIG. 1 is a block schematic diagram illustrating a DRAM device 100. The DRAM 100 is shown to include eight memory arrays 102a-102h, each having an associated sense amplifier bank 104a-104h. During an active cycle of the DRAM 100, memory cells within the memory arrays (102a-102h) are coupled to the sense amplifier banks (104a-104h). For example, in a read and refresh operation, memory cell data signals are amplified by the sense amplifier banks (104a-104h) and rewritten (refreshed) back into the memory cells. In the case of a read operation, the amplified data signal can be subsequently provided as output data. In a write operation, data is written into the memory cells by the sense amplifier banks (104a-104h) according to externally applied data.
The prior art DRAM 100 of FIG. 1 illustrates an example of a DRAM IC that utilizes a reduced array voltage. Reduced array voltages are used to improve the power consumption characteristics and reliability of a DRAM IC. Referring now to FIG. 2, a portion of a memory cell array 102 and a sense amplifier bank 104 are shown in a schematic diagram. The memory cell array 102 includes a pair of bit lines 200a and 200b, and a DRAM memory cell 202. The memory cell 202 includes an n-channel metal-insulator-semiconductor (MOS) pass transistor N200 coupled to a storage capacitor C200. The gate of transistor N200 is coupled to a word line 204, which is driven by a WL signal. The bit line pair (200a and 200b) is coupled to the sense amplifier bank 104 by a pair of transfer gates transistors N202 and N204. The gates of transistors N202 and N204 are driven by a signal TG. The magnitude of the voltage applied to the gate of transistors N200 can impact the reliability of the DRAM. The higher the voltage, the greater that chance that insulators surrounding the word line, particularly gate insulators, will break down and create a short circuit condition.
The portion of the sense amplifier bank 104 shown in FIG. 2 includes one sense amplifier 206, that has a high sense amplifier supply voltage, shown as SDP, and a low sense amplifier supply voltage, VSS. The sense amplifier 206 is activated by a sense amplifier enable signal /SAEN.
In order to reduce any threshold voltage drop caused by the pass transistors in a DRAM memory cell array, in operation, the gates of pass transistors are driven to a voltage that is higher than the voltage used by the sense amplifiers to refresh (or write) data in the storage capacitor. Initially, DRAM ICs included sense amplifiers which used the power supply voltage levels in refresh operations, and "booting" circuits which utilized a higher than power supply voltages to drive pass transistors. As thinner dielectrics are used, the reliability concerns noted above can come into play, placing a limit on the magnitude of the voltage that may be placed on a pass transistor gate. Thus, rather than use a booted voltage, the high power supply voltage of the DRAM IC is used to drive pass transistors, and a voltage less than a power supply voltage is used to refresh data. The same approach used to drive the pass transistors could be used to drive transfer gates, such as N202 and N204 in FIG. 2.
A drawback to using a reduced sense amplifier supply voltage is the reduced speed at which the sense amplifier will drive a bit line to a high voltage. One way to overcome this drawback, is to use a variable sense amplifier supply voltage. During the initial portion of a read/refresh operation, the sense amplifiers are supplied with the high power supply voltage to provide a rapid initial sense amplifier response. At a later portion in the read/refresh operation, the reduced voltage is provided to the sense amplifier. This is the approach illustrated by the DRAM of FIGS. 1 and 2.
In the case of the DRAM 100 of FIGS. 1 and 2, the high power supply voltage is designated as VDD, and the reduced array voltage is designated as VDL. Thus, the word line signal WL and the TG signal are driven between a low power supply voltage VSS and the high power supply voltage VDD. In addition, while the low sense amplifier supply voltage is VSS, the high sense amplifier supply voltage is SDP. The SDP voltage varies between the VDD voltage level and the VDL voltage level.
Referring back to FIG. 1, it is shown that in the DRAM 100, the sense amplifier banks (104a-104h) each receive an enable signal, /SAEN. When the /SAEN signal is low, the sense amplifier banks (104a-104h) are enabled, and when /SAEN signal is high, the sense amplifier banks (104a-104h) are disabled. Each sense amplifier bank (104a-104h) also receives the sense amplifier supply voltage SDP. The SDP voltage is generated by a supply switch circuit 106 activated by a supply switch signal /SDP.sub.-- EN. When the /SDP.sub.-- EN signal is high, a VDL supply voltage 108 is used to generate the SDP voltage. When the /SDP.sub.-- EN signal is low, a VDD supply voltage 110 is used to generate the SDP voltage.
A drawback to the prior art DRAM 100 arises from the propagation delay within the DRAM 100. In the event the single switching signal /SDP.sub.-- EN is not properly timed with the activation of the sense amplifiers by the /SAEN signal, the voltages on the bit lines within different memory array (102a-102h) may not be uniform. This drawback is best illustrated by the timing diagram of FIG. 3.
FIG. 3 is a timing diagram illustrating the operation and drawbacks of the prior art DRAM IC set forth in FIGS. 1 and 2. Three /SAEN signals and their corresponding bit line pair responses are illustrated. An ideal response is shown by waveforms 300, an "undershoot" response is shown by waveforms 302, and an overshoot response is shown by waveforms 304. The ideal response waveforms 300 will be discussed first. At time t0, a word line (shown as 204 in FIG. 2) rises from VSS to VDD, turning on a pass transistor (N200 in FIG. 2). This action results in a differential voltage developing between bit line pairs (BL and /BL). For the waveforms of FIG. 3, it is assumed that the memory cell coupled to bit line BL is charged to a positive potential, and so bit line BL begins to rise at time t0. Also at the same time, the /SDP.sub.-- EN falls from VDD to VSS. Referring back to FIG. 1, it is recalled that when the /SDP.sub.-- EN falls from VDD to VSS, the supply switch circuit 106 switches from the VDL voltage supply 108 to the VDD voltage supply 110. Consequently, the sense amplifier supply voltage SDP rises at time t0, from VDL to VDD. This provides the initial fast sensing operation for the sense amplifier banks (104a-104h).
At time t1, the sense amplifier enable signal /SAEN falls from VDD to VSS. This enables the sense amplifiers. One bit line is driven to the sense amplifier low supply voltage (VSS) while the other is driven toward the sense amplifier high supply voltage (at time t1, this is VDD).
At time t2, the /SDP.sub.-- EN falls from the voltage VDD to the voltage VSS. By operation of the supply switch circuit 106, the SDP voltage returns to the lower VDL supply voltage. The timing of the falling edge of the /SDP.sub.-- EN signal is selected to coincide with the voltage of the BL reaching VDL. In other words, the time period from t1 to t2 is selected to be the time required for a sense amplifier with a supply voltage at VDD to charge bit line BL to the voltage VDL.
At time t3, the sense operation concludes with the WL signal returning to the VSS voltage. At the same time, the /SAEN signal goes from the VDD voltage to the VSS voltage, and an EQ signal rises from the VSS voltage to the VDD voltage. The EQ signal couples the bit lines together, to equalize the bit line potential. In the waveform 300 in FIG. 3, the equalization voltage is shown as VBLR, and is equal to 1/2 VDL, assuming VSS=0 volts.
The undershoot waveform 302 illustrates a case in which the sense amplifier enable signal /SAEN occurs later in time than the /SDP.sub.-- EN signal. This may arise due to a propagation delay in the /SAEN signal. For example, referring back to FIG. 1, the ideal waveform 300 may represent the response of memory array 102h and sense amplifier bank 104h, while the undershoot waveform 302 may represent the response to memory array 102a and sense amplifier bank 104a. Because the sense amplifier bank 104a is physically situated further from the source of the /SAEN signal than sense amplifier 104h, the /SAEN signal as applied to sense amplifier bank 104a will be delayed with respect to sense amplifier bank 104h.
Referring once again to FIG. 3, it is shown that between times t0 and t1 the waveforms 302 have the same response as waveforms 300. The WL signal goes high, and a memory cell is coupled to one of the bit lines. As in the case of waveform 300 it is assumed that a positively charged memory cell capacitor is coupled to bit line BL.
Unlike the ideal response of wavefonns 300, in the undershoot example of waveforms 302, due to the delay between the falling edge of the /SAEN signal and the falling edge of the /SDP.sub.-- EN signal, the sense amplifiers will be connected to the VDD voltage supply for a smaller amount of time than in the ideal case of waveforms 300. Consequently, at time t2, the voltage of bit line BL is at a potential less than the VDL voltage level when the sense amplifier switches from the VDD level to the VDL level.
Unlike the ideal response of waveforms 300, which maintains a VDL level between times t2 and t3, in the undershoot example of waveforms 302, between times t2 and t3, the bit line charges, at a slower rate, toward the VDL level. This arrangement is undesirable, as the data within the memory cell is refreshed during this time period. Because the voltage level is less than VDL, the storage capacitor will be charged by a voltage that is less than VDL, which may cause data retention failures in the memory cells.
At time t3, the bit lines of waveforms 302 are equalized. Because bit line BL has not yet reached the VDL level, the resulting equalization voltage is less than the BLR (1/2 VDD) potential. In the event the bit lines are connected to a 1/2 VDD precharge voltage, current will be drawn as the bit lines are brought back up to the BLR potential. Further, in the event the bit lines cannot be brought back to the BLR potential by the next read cycle, an erroneous read operation may result.
The overshoot waveforms 304 illustrates a case in which the sense amplifier enable signal /SAEN occurs earlier in time than the /SDP--EN signal. This may arise due to a propagation delay in the /SDP--EN signal, and serves to show the undesirability of having sense amplifiers drive bit lines above the array voltage VDL.
As in the case of waveforms 300 and 302, for the overshoot case of waveforms 304, it assumed that memory cell having a charged capacitor is coupled to bit line BL. Thus at time to, bit line BL begins to rise in potential.
Referring once again to FIG. 3, in the overshoot case of waveforms 304, the low-going edge of the /SAEN signal precedes the low-going edge of the /SDP.sub.-- EN signal, resulting in the VDD supply being connected to the sense amplifier for a longer period of time than the ideal case. Consequently, from time t1 to t2, the voltage on bit line BL reaches, and then exceeds the VDL voltage level.
At time t2, as shown in waveforms 304, the SDP switches from the VDD level, back down to VDL. The bit line BL will then discharge toward VDL between times t2 and t3. This results in unwanted current consumption in this time period.
At time t3, the bit lines of waveforms 304 are equalized. Because bit line BL exceeds the VDL level, the resulting equalization voltage is greater than the BLR (1/2 VDD) potential. In a similar manner to the undershoot case 302, in the event the bit lines are connected to a 1/2 VDD precharge voltage, current will be drawn as the bit lines are brought back down to the BLR potential. In addition, in the event the bit lines cannot be brought back down to the BLR potential by the next read cycle, an erroneous read operation may result.
It would be desirable to provide a memory IC having a reduced array voltage that does not suffer from the adverse affects of timing differences between a switched sense amplifier power supply and other timed operations in the memory IC.